1. Technical Field
The present invention relates to a semiconductor device having a local interconnect structure and a fabrication method for the same.
2. Background Art
In recent years, with the trend toward finer semiconductor devices, gate electrodes tend to have larger contact resistance and wiring resistance. To address this problem, a local interconnect structure is used to connect a gate electrode with a source/drain region to thereby reduce wiring resistance (see Japanese Laid-Open Patent Publication No. 2007-150244, for example). The local interconnect structure as used herein refers to routing, including a shared contact plug, that connects an element and an interconnect mutually without use of global wiring formed in a wiring layer.
In particular, in a metal-insulator-semiconductor (MIS) transistor constituting a static random access memory (SRAM) cell, such a local interconnect structure is very effective because with use of the local interconnect structure, not only the reduction in wiring resistance but also reduction in the size of the SRAM cell can be attained.
FIG. 10 shows a cross-sectional configuration of a conventional semiconductor device having a shared contact. As shown in FIG. 10, an active region 107 surrounded with an isolation region 106 is formed in a semiconductor substrate 101. A MIS transistor 110 is formed in the active region 107. A gate electrode 103A of the MIS transistor 110 is formed on the active region 107 with a gate insulating film 102A interposed therebetween. Source/drain regions 104a and 104b are formed in portions of the active region 107 located on both sides of the gate electrode 103A. Sidewalls 105A are formed on both side faces of the gate electrode 103A.
A gate interconnect 103B is formed on a portion of the active region 107 located on the side of the source/drain region 104a opposite to the side thereof closer to the gate electrode 103A, with an insulating film 102B interposed therebetween. Sidewalls 105B are formed on both side faces of the gate interconnect 103B.
An underlying insulating film 120 and an interlayer insulating film 121 are formed on the semiconductor substrate 101 to cover the gate electrode 103A and the gate interconnect 103B. A shared contact plug 108 connected to both the source/drain region 104a and the gate interconnect 103B and a contact plug 109 connected to the source/drain region 104b are formed through the underlying insulating film 120 and the interlayer insulating film 121.
With the connection of the source/drain region 104a with the gate interconnect 103B via the shared contact plug 108, it is possible to not only reduce wiring resistance but also reduce the occupation area, compared with a configuration in which contacts are separately formed for the source/drain region 104a and the gate interconnect 103B and are connected to each other in a wiring layer. Hence, semiconductor devices adopting a local interconnect structure such as the shared contact plug can be downsized without increasing wiring resistance.